LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ADDER4 IS 
    PORT(
        CIN: IN STD_LOGIC;
        A, B: IN STD_LOGIC_VECTOR(3 downto 0);
        CO : OUT STD_LOGIC;
        S: OUT STD_LOGIC_VECTOR(3 downto 0));
END ADDER4;

ARCHITECTURE RTL OF ADDER4 IS 
    SIGNAL ST,COT: STD_LOGIC_VECTOR(3 downto 0);
    COMPONENT ADDER 
    PORT(
        CIN, A, B: IN STD_LOGIC ;
        S, CO : OUT STD_LOGIC);
    END COMPONENT;
BEGIN 
    CO <= COT(3);
    S <= ST;
    U1: ADDER PORT MAP('0',A(0),B(0),ST(0),COT(0));
    U2: ADDER PORT MAP(COT(0),A(1),B(1),ST(1),COT(1));
    U3: ADDER PORT MAP(COT(1),A(2),B(2),ST(2),COT(2));
    U4: ADDER PORT MAP(COT(2),A(3),B(3),ST(3),COT(3));

END RTL;